primitive simulink blocks "inport" and "outport  (MathWorks Inc)

Journal: bioRxiv

Article Title: The BrightEyes-TTM: an Open-Source Time-Tagging Module for Single-Photon Microscopy

doi: 10.1101/2021.10.11.463950

Figure Lengend Snippet: a Flash TDC module comprenshive of a hit-filter and tapped-delay-line made up by inbuilt FPGA CARRY delay elements (top). Latch barrier to sample and stabilize the tapped-delay-line readings (i.e. Δ T START ( ch ) or Δ T STOP ) (middle). Thermometer to binary encoder to translate the tapped-delay-line readings into a binary form (bottom). b Example of thermometer-to-binary working principle: tapped-delay-line readings are converted into binary number for a more compact and efficient data representation.

Article Snippet: A specific Xilinx FPGA primitive function block known as CARRY (CARR4 or CARRY8 depending on the FPGA family) was used as a fundamental delay block to build the tapped delay line, formed by connecting multiple CARRY blocks.

Techniques:

Journal: Sensors (Basel, Switzerland)

Article Title: Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

doi: 10.3390/s140202860

Figure Lengend Snippet: Resource usage and maximum working frequency of different modules (description in text).

Article Snippet: The standard abbreviations for resources available in Xilinx FPGA devices are used: FF — flip-flops or registers, LUT 6 — look-up table with six inputs and one output, SLICE — slice cells of FPGA, BRAM 18 and 36 — the 2kB or 4kB basic FPGA Block RAM primitive memories, DSP48 - hardware digital signal processing blocks.

Techniques:

Journal: Sensors (Basel, Switzerland)

Article Title: Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

doi: 10.3390/s140202860

Figure Lengend Snippet: Processing times in milliseconds for Core i7 2600K 3.4 GHz processor and hardware implementations in Virtex 7 XC7VX980T device.

Article Snippet: The standard abbreviations for resources available in Xilinx FPGA devices are used: FF — flip-flops or registers, LUT 6 — look-up table with six inputs and one output, SLICE — slice cells of FPGA, BRAM 18 and 36 — the 2kB or 4kB basic FPGA Block RAM primitive memories, DSP48 - hardware digital signal processing blocks.

Techniques:

Journal: Sensors (Basel, Switzerland)

Article Title: Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

doi: 10.3390/s140202860

Figure Lengend Snippet: Working system. Camera, FPGA evaluation board and LCD monitor displaying the result. ( Left ), optical flow obtained for poster tube rotation. ( Right ), person waving hands in opposite directions.

Article Snippet: The standard abbreviations for resources available in Xilinx FPGA devices are used: FF — flip-flops or registers, LUT 6 — look-up table with six inputs and one output, SLICE — slice cells of FPGA, BRAM 18 and 36 — the 2kB or 4kB basic FPGA Block RAM primitive memories, DSP48 - hardware digital signal processing blocks.

Techniques: